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Pull requests: intel/intel-xpu-backend-for-triton
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[LoadOpToBlockIOConversion] Refactor block load codegen for regular pointer
#5242
opened Oct 1, 2025 by
whitneywhtsang
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[LoadOpToBlockIOConversion] Adjust
vBlock
to fit the constancy of mask
#5239
opened Oct 1, 2025 by
whitneywhtsang
•
Draft
[Draft] Add a new stage to generate
zebin
to align CUDA stages in triton.compile
#5189
opened Sep 25, 2025 by
chengjunlu
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[Draft] Support the globaltimer and smid on Intel Arch
#4816
opened Jul 31, 2025 by
chengjunlu
•
Draft
A tracking utility for gathering the compile and/or runtime time, size, profiling and other statistics
#4777
opened Jul 25, 2025 by
AndreyPavlenko
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[LoadStoreToLLVM] Refactor the 2D block load lowering.
#4615
opened Jul 4, 2025 by
chengjunlu
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[BACKEND] Enhance the remove layout implementation to reduce the duplicated values with different layout in scf.for.
#4527
opened Jun 18, 2025 by
chengjunlu
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Clean up Intel specific code in the common TritonGPU dialect source file.
upstream: triton
#4469
opened Jun 10, 2025 by
chengjunlu
•
Draft
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