[PowerPC] Implement vector uncompress instructions #150702
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@llvm/pr-subscribers-mc @llvm/pr-subscribers-backend-powerpc Author: Lei Huang (lei137) ChangesImplement the set of vector uncompress instructions:
Full diff: https://github.com/llvm/llvm-project/pull/150702.diff 4 Files Affected:
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 1ac91fadf6582..0693b4537178f 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -45,6 +45,20 @@ multiclass XOForm_RTAB5_L1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
}
}
+class VXForm_VRTAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
+ list<dag> pattern> : I<4, OOL, IOL, asmstr, NoItinerary> {
+ bits<5> VRT;
+ bits<5> VRA;
+ bits<5> VRB;
+
+ let Pattern = pattern;
+
+ let Inst{6 -10} = VRT;
+ let Inst{11 -15} = VRA;
+ let Inst{16 -20} = VRB;
+ let Inst{21 -31} = xo;
+}
+
let Predicates = [IsISAFuture] in {
defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
(ins g8rc:$RA, g8rc:$RB, u1imm:$L),
@@ -85,4 +99,21 @@ let Predicates = [HasVSX, IsISAFuture] in {
(ins vsrprc:$XTp, memr:$RA, g8rc:$RB),
"stxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>;
}
+
+ def VUCMPRHN : VXForm_VRTAB5<3, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
+ "vucmprhn $VRT, $VRA, $VRB", []>;
+ def VUCMPRLN : VXForm_VRTAB5<67, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
+ "vucmprln $VRT, $VRA, $VRB", []>;
+ def VUCMPRHB
+ : VXForm_VRTAB5<131, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
+ "vucmprhb $VRT, $VRA, $VRB", []>;
+ def VUCMPRLB
+ : VXForm_VRTAB5<195, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
+ "vucmprlb $VRT, $VRA, $VRB", []>;
+ def VUCMPRHH
+ : VXForm_VRTAB5<259, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
+ "vucmprhh $VRT, $VRA, $VRB", []>;
+ def VUCMPRLH
+ : VXForm_VRTAB5<323, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
+ "vucmprlh $VRT, $VRA, $VRB", []>;
}
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
index 4bea42243f83b..e944771f8a298 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
@@ -195,3 +195,21 @@
#CHECK: dmxxsha224256pad 0, 1
0xf0,0x18,0x0e,0x94
+
+#CHECK: vucmprhn 0, 2, 3
+0x10,0x02,0x18,0x03
+
+#CHECK: vucmprln 3, 5, 6
+0x10,0x65,0x30,0x43
+
+#CHECK: vucmprhb 1, 3, 6
+0x10,0x23,0x30,0x83
+
+#CHECK: vucmprlb 2, 4, 5
+0x10,0x44,0x28,0xC3
+
+#CHECK: vucmprlh 2, 4, 5
+0x10,0x44,0x29,0x43
+
+#CHECK: vucmprhh 1, 3, 6
+0x10,0x23,0x31,0x03
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
index 233693e67292e..e146d9ec32fc7 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
@@ -189,3 +189,21 @@
#CHECK: dmxxsha224256pad 0, 1
0x94,0x0e,0x18,0xf0
+
+#CHECK: vucmprhn 0, 2, 3
+0x03,0x18,0x02,0x10
+
+#CHECK: vucmprln 3, 5, 6
+0x43,0x30,0x65,0x10
+
+#CHECK: vucmprhb 1, 3, 6
+0x83,0x30,0x23,0x10
+
+#CHECK: vucmprlb 2, 4, 5
+0xC3,0x28,0x44,0x10
+
+#CHECK: vucmprlh 2, 4, 5
+0x43,0x29,0x44,0x10
+
+#CHECK: vucmprhh 1, 3, 6
+0x03,0x31,0x23,0x10
diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
index cba93291e4595..f3b86ae8dff72 100644
--- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
+++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
@@ -282,3 +282,27 @@
dmxxsha224256pad 0, 1
#CHECK-BE: dmxxsha224256pad 0, 1 # encoding: [0xf0,0x18,0x0e,0x94]
#CHECK-LE: dmxxsha224256pad 0, 1 # encoding: [0x94,0x0e,0x18,0xf0]
+
+ vucmprhn 0, 2, 3
+#CHECK-BE: vucmprhn 0, 2, 3 # encoding: [0x10,0x02,0x18,0x03]
+#CHECK-LE: vucmprhn 0, 2, 3 # encoding: [0x03,0x18,0x02,0x10]
+
+ vucmprln 3, 5, 6
+#CHECK-BE: vucmprln 3, 5, 6 # encoding: [0x10,0x65,0x30,0x43]
+#CHECK-LE: vucmprln 3, 5, 6 # encoding: [0x43,0x30,0x65,0x10]
+
+ vucmprhb 1, 3, 6
+#CHECK-BE: vucmprhb 1, 3, 6 # encoding: [0x10,0x23,0x30,0x83]
+#CHECK-LE: vucmprhb 1, 3, 6 # encoding: [0x83,0x30,0x23,0x10]
+
+ vucmprlb 2, 4, 5
+#CHECK-BE: vucmprlb 2, 4, 5 # encoding: [0x10,0x44,0x28,0xc3]
+#CHECK-LE: vucmprlb 2, 4, 5 # encoding: [0xc3,0x28,0x44,0x10]
+
+ vucmprlh 2, 4, 5
+#CHECK-BE: vucmprlh 2, 4, 5 # encoding: [0x10,0x44,0x29,0x43]
+#CHECK-LE: vucmprlh 2, 4, 5 # encoding: [0x43,0x29,0x44,0x10]
+
+ vucmprhh 1, 3, 6
+#CHECK-BE: vucmprhh 1, 3, 6 # encoding: [0x10,0x23,0x31,0x03]
+#CHECK-LE: vucmprhh 1, 3, 6 # encoding: [0x03,0x31,0x23,0x10]
|
diggerlin
reviewed
Jul 29, 2025
| @@ -45,6 +45,20 @@ multiclass XOForm_RTAB5_L1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, | |||
| } | |||
| } | |||
|
|
|||
| class VXForm_VRTAB5<bits<11> xo, dag OOL, dag IOL, string asmstr, | |||
| list<dag> pattern> : I<4, OOL, IOL, asmstr, NoItinerary> { | |||
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I am curious that there is no opCode in the new define instruction ?
There was a problem hiding this comment.
part of the the class it's inheriting from : I<4,...>. The opcode for this class of instructions is 4.
diggerlin
approved these changes
Jul 29, 2025
| @@ -45,6 +45,20 @@ multiclass XOForm_RTAB5_L1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, | |||
| } | |||
| } | |||
|
|
|||
| class VXForm_VRTAB5<bits<11> xo, dag OOL, dag IOL, string asmstr, | |||
| list<dag> pattern> : I<4, OOL, IOL, asmstr, NoItinerary> { | |||
| bits<5> VRA; | ||
| bits<5> VRB; | ||
|
|
||
| let Pattern = pattern; |
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nit: since the value of the pattern are [] in all the following definition, I do not think we need to introduce the pattern parameter.
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this should be kept so we can easily add patterns to these instructions definitions in the future when we define intrinsic or identify specific patterns that should be matched to these.
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Implement the set of vector uncompress instructions: