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[PowerPC] Implement vector uncompress instructions #150702

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[PowerPC] Implement vector uncompress instructions #150702

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f9e2d2b
Implement vector uncompress instructions
lei137 Jul 25, 2025
95870ef
add encoding tests
lei137 Jul 25, 2025
6a0dc87
add more encoding tests
lei137 Jul 25, 2025
8c921fb
add more encoding tests
lei137 Jul 25, 2025
5b58786
fix xo encoding for vucmprhh
lei137 Jul 25, 2025
3486f50
add last encoding test
lei137 Jul 25, 2025
962ff02
remove accidental new file
lei137 Jul 25, 2025
49fe55f
apply clang-format
lei137 Jul 25, 2025
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31 changes: 31 additions & 0 deletions llvm/lib/Target/PowerPC/PPCInstrFuture.td
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Original file line number Diff line number Diff line change
Expand Up @@ -45,6 +45,20 @@ multiclass XOForm_RTAB5_L1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
}
}

class VXForm_VRTAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
list<dag> pattern> : I<4, OOL, IOL, asmstr, NoItinerary> {
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I am curious that there is no opCode in the new define instruction ?

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part of the the class it's inheriting from : I<4,...>. The opcode for this class of instructions is 4.

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thanks , I see

bits<5> VRT;
bits<5> VRA;
bits<5> VRB;

let Pattern = pattern;
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@diggerlin diggerlin Jul 29, 2025 •
edited
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nit: since the value of the pattern are [] in all the following definition, I do not think we need to introduce the pattern parameter.

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this should be kept so we can easily add patterns to these instructions definitions in the future when we define intrinsic or identify specific patterns that should be matched to these.


let Inst{6 -10} = VRT;
let Inst{11 -15} = VRA;
let Inst{16 -20} = VRB;
let Inst{21 -31} = xo;
}

let Predicates = [IsISAFuture] in {
defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
(ins g8rc:$RA, g8rc:$RB, u1imm:$L),
Expand Down Expand Up @@ -85,4 +99,21 @@ let Predicates = [HasVSX, IsISAFuture] in {
(ins vsrprc:$XTp, memr:$RA, g8rc:$RB),
"stxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>;
}

def VUCMPRHN : VXForm_VRTAB5<3, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
"vucmprhn $VRT, $VRA, $VRB", []>;
def VUCMPRLN : VXForm_VRTAB5<67, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
"vucmprln $VRT, $VRA, $VRB", []>;
def VUCMPRHB
: VXForm_VRTAB5<131, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
"vucmprhb $VRT, $VRA, $VRB", []>;
def VUCMPRLB
: VXForm_VRTAB5<195, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
"vucmprlb $VRT, $VRA, $VRB", []>;
def VUCMPRHH
: VXForm_VRTAB5<259, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
"vucmprhh $VRT, $VRA, $VRB", []>;
def VUCMPRLH
: VXForm_VRTAB5<323, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
"vucmprlh $VRT, $VRA, $VRB", []>;
}
18 changes: 18 additions & 0 deletions llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
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Expand Up @@ -195,3 +195,21 @@

#CHECK: dmxxsha224256pad 0, 1
0xf0,0x18,0x0e,0x94

#CHECK: vucmprhn 0, 2, 3
0x10,0x02,0x18,0x03

#CHECK: vucmprln 3, 5, 6
0x10,0x65,0x30,0x43

#CHECK: vucmprhb 1, 3, 6
0x10,0x23,0x30,0x83

#CHECK: vucmprlb 2, 4, 5
0x10,0x44,0x28,0xC3

#CHECK: vucmprlh 2, 4, 5
0x10,0x44,0x29,0x43

#CHECK: vucmprhh 1, 3, 6
0x10,0x23,0x31,0x03
18 changes: 18 additions & 0 deletions llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
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Expand Up @@ -189,3 +189,21 @@

#CHECK: dmxxsha224256pad 0, 1
0x94,0x0e,0x18,0xf0

#CHECK: vucmprhn 0, 2, 3
0x03,0x18,0x02,0x10

#CHECK: vucmprln 3, 5, 6
0x43,0x30,0x65,0x10

#CHECK: vucmprhb 1, 3, 6
0x83,0x30,0x23,0x10

#CHECK: vucmprlb 2, 4, 5
0xC3,0x28,0x44,0x10

#CHECK: vucmprlh 2, 4, 5
0x43,0x29,0x44,0x10

#CHECK: vucmprhh 1, 3, 6
0x03,0x31,0x23,0x10
24 changes: 24 additions & 0 deletions llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
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Expand Up @@ -282,3 +282,27 @@
dmxxsha224256pad 0, 1
#CHECK-BE: dmxxsha224256pad 0, 1 # encoding: [0xf0,0x18,0x0e,0x94]
#CHECK-LE: dmxxsha224256pad 0, 1 # encoding: [0x94,0x0e,0x18,0xf0]

vucmprhn 0, 2, 3
#CHECK-BE: vucmprhn 0, 2, 3 # encoding: [0x10,0x02,0x18,0x03]
#CHECK-LE: vucmprhn 0, 2, 3 # encoding: [0x03,0x18,0x02,0x10]

vucmprln 3, 5, 6
#CHECK-BE: vucmprln 3, 5, 6 # encoding: [0x10,0x65,0x30,0x43]
#CHECK-LE: vucmprln 3, 5, 6 # encoding: [0x43,0x30,0x65,0x10]

vucmprhb 1, 3, 6
#CHECK-BE: vucmprhb 1, 3, 6 # encoding: [0x10,0x23,0x30,0x83]
#CHECK-LE: vucmprhb 1, 3, 6 # encoding: [0x83,0x30,0x23,0x10]

vucmprlb 2, 4, 5
#CHECK-BE: vucmprlb 2, 4, 5 # encoding: [0x10,0x44,0x28,0xc3]
#CHECK-LE: vucmprlb 2, 4, 5 # encoding: [0xc3,0x28,0x44,0x10]

vucmprlh 2, 4, 5
#CHECK-BE: vucmprlh 2, 4, 5 # encoding: [0x10,0x44,0x29,0x43]
#CHECK-LE: vucmprlh 2, 4, 5 # encoding: [0x43,0x29,0x44,0x10]

vucmprhh 1, 3, 6
#CHECK-BE: vucmprhh 1, 3, 6 # encoding: [0x10,0x23,0x31,0x03]
#CHECK-LE: vucmprhh 1, 3, 6 # encoding: [0x03,0x31,0x23,0x10]