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@micprog micprog commented Apr 22, 2025

Contributions:

  • ci: Bump various Github actions
  • hw: Connect cluster peripherals using APB interface (AXI to AXI-Lite to APB)
  • treewide: Replace hjson and reggen with rdl and peakrdl respectively

@colluca
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colluca commented Apr 23, 2025

Simple question, why? 😁

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micprog commented Apr 23, 2025

Simple question, why? 😁

SystemRDL together with PeakRDL provides great infrastructure for register files, and especially can tie together these address maps hierarchically, allowing for a full view of an SoC. The language is properly specified and more widely accepted than opentitan's hjson format. Furthermore, most industry-standard IPs use APB as a configuration interface, which is also directly supported here in favor of register interface (feel free look into adding register_interface ports to peakrdl-regblock if you prefer this). Ensuring the registers are generated from the rdl description further ensures a single source of truth for the system's mapping. Pulling together rdl files, adding memory blocks, and tying these together allows for direct checking of address map collisions, and ultimately provides a top-level view of a system's address space, something that would require a significant amount of manual work with the current infrastructure.

@colluca
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colluca commented Apr 23, 2025

SystemRDL together with PeakRDL provides great infrastructure for register files, and especially can tie together these address maps hierarchically, allowing for a full view of an SoC. The language is properly specified and more widely accepted than opentitan's hjson format.

I see now that it's an Accelera standard. Cool, thanks @micprog :)

@micprog micprog marked this pull request as ready for review May 26, 2025 18:11
@fischeti
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fischeti commented May 30, 2025

Currently, some tests are failing because the .bss section in the tests is very large. The .bss section is initialized in the beginning with the DMA and the zero memory. But if the BSS section is too large, the DMA transfers will overflow the zero memory address range. It can be fixed in SW, but since we anyway will get rid of the zero memory in #238 it might make more sense to wait for this PR to be merged.

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Thanks for the contribution @micprog! It mostly LGTM, I just have some minor questions for you in the following review. Regarding the suggested changes I could also apply these myself.

@colluca colluca force-pushed the rdl branch 8 times, most recently from 0604dd2 to a2a8508 Compare June 14, 2025 12:24
@colluca colluca changed the base branch from main to develop June 14, 2025 12:25
@colluca colluca force-pushed the rdl branch 3 times, most recently from 3e45ec5 to f7d7ef7 Compare June 14, 2025 13:58
@colluca colluca force-pushed the rdl branch 2 times, most recently from 9e4da51 to b2248a0 Compare July 2, 2025 08:50
@colluca colluca merged commit 201bba3 into develop Jul 4, 2025
20 of 21 checks passed
@colluca colluca deleted the rdl branch July 4, 2025 12:37
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3 participants