processor-design

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Here are 95 public repositories matching this topic...

katef / eurorack-cpu

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A CPU implemented in a modular synthesizer

modular synthesizer cpu-emulator processor-design

Updated Mar 20, 2022

zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial

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Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…

cpu processor simd verilog alu adder instruction-set-architecture cadence-virtuoso multiplier verilog-project processor-design

Updated Jul 17, 2022
Verilog

peilin-chen / Zhulong-RISCV-CPU

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CPU Design Based on RISCV ISA

integrated-circuits processor-design

Updated Jun 14, 2024
Verilog

tscheipel / HaDes-V

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HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

processor-architecture pipelines riscv vivado systemverilog computer-architecture gtkwave system-verilog university-course risc-v c-programming rv32i open-education verilator open-educational-resources processor-design assembly-programming hardware-software-codesign microcontroller-design

Updated Jun 5, 2025
SystemVerilog

shehanmunasinghe / tinyGPU

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tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog

gpu simd systemverilog hdl computer-organization processor-design

Updated Jul 14, 2021
SystemVerilog

aofarmakis / Nibbling-bits

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Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.

assembly assembler verilog computer-architecture instruction-set-architecture computer-organization hardware-description-language processor-design single-cycle-processor

Updated Dec 7, 2024
Verilog

alirezakay / RISC-CPU

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A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

processor-architecture cpu vhdl isa cpu-model instruction-set-architecture mips-processor vhdl-modules risc-processor vhdl-code cpu-architecture multi-cycle processor-design

Updated Jun 19, 2021
VHDL

mpskex / chisel-npu

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Chisel implementation of Neural Processing Unit for System on the Chip

chisel3 system-on-chip processor-design npu

Updated Aug 29, 2025
Scala

KevinWang96 / Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chip

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EE577b-Course-Project

verilog-hdl multiprocessor processor-design networkonchip synopsys-dc cadence-ncverilog cadence-conformal

Updated May 6, 2020
Verilog

Amey-Thakur / COMPUTER-ORGANIZATION-AND-ARCHITECTURE-AND-PROCESSOR-ARCHITECTURE-LAB

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CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] <Semester IV>

computer-science processor-architecture engineering computer-engineering textbooks computer-organization computer-organisation processor-design computer-organisation-architechure computer-organization-lab computer-organization-and-design computer-organ ameythakur amey megasatish

Updated Mar 13, 2024
C

darklife / udarkrisc

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u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV

cpu fpga core processor rtl verilog risc softcore processor-design

Updated Jul 25, 2023
Verilog

qossayrida / PipelineProcessorDesign

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Design and verification of a simple pipelined RISC processor in Verilog, featuring a five-stage pipeline and custom ISA.

verilog pipelining computer-architecture risc processor-design

Updated Jul 15, 2024
Verilog

AnkurRyder / 8085-Processor

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8-bit RISC Processor on Logisim

circuit-simulator logisim processor-design

Updated Oct 1, 2020

daniel-santos-7 / leaf

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Um pequeno processador RISC-V de 32 bits desenvolvido com a linguagem de descrição VHDL.

fpga riscv fpga-soc risc-v wishbone-bus processor-design

Updated Apr 23, 2023
VHDL

Awais-Asghar / Single-Cycle-RISC-V-Processor-Implemented-on-FPGA

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An FPGA-based single-cycle RISC-V processor (RV32I) implemented in SystemVerilog. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. This project is ideal for learning computer architecture, digital design, and RISC-V ISA implementation.

fpga vivado computer-architecture system-verilog risc-v cpu-architecture processor-design single-cycle-processor digital-design-and-computer-organization rv32i-processor

Updated Jul 21, 2025
SystemVerilog

Sooryakiran / Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project

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Implementation of Vector Reduce Min and Vector Negation ASIC Hardware, plus a toy CPU, memory and custom ISA for demo. Can be compiled to Verilog. Demos include fib series computations using custom ISA (and custom assembly) and some vector programs.